1. Field of the Invention
The present invention relates to a test control circuit for a scan path, and more particularly, to a circuit for controlling a setting and resetting of a flipflop.
2. Description of Related Art
Integrated circuits using a conventional scan path have been so constructed that, a set terminal and a reset terminal of flipflops are controlled to be forcibly maintained in a disable condition during a period in which a scan test is being performed, in order to protect a shift data applied to the set terminal and the reset terminal of flipflops in the process of the scan shifting.
For example, one conventional scan path is so constructed that, in the scan test, an input terminal for controlling a reset terminal of a scan path flipflop is fixed to a value, for example "1", which never sets or resets the flipflop regardless of whether it is either in a scan shifting or at the time of testing the normal circuit. This control makes it possible to avoid the shift data from being broken in the scan shifting. However, this construction cannot test the set and the reset of the flipflop. In the case that an internal circuit of an associated reset signal generating circuit is composed of only a combinational circuit, if the values are appropriately set, it cannot be said that it is not possible to test the set terminal and the reset terminal. However, if the reset signal generating circuit includes a sequential circuit, it is impossible to test the set terminal and the reset terminal.
In the control of the conventional scan path, accordingly, since the set terminal and the reset terminal of the scan flipflop are brought by a control signal into a disable condition in the process of testing the scan path, it is not possible to test, in the process of the scan path test, the set terminal and the reset terminal themselves of the scan path flipflop and a circuit for propagating the output to only the set terminal or the reset terminal of the scan path flipflop.